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Prof. Omer Khan Receives SRC grant on “Data Locality-Based Adaptive Shared Memory Architecture for Massive Data Applications”

Data Locality-Based Adaptive Shared Memory Architecture for Massive Data Applications
Executive Summary: Next generation multi-core/SOC applications, such as online network classification, will exhibit massive data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance to the future of the semiconductor industry. We propose a novel shared memory architecture that enables seamless  adaptation between private and logically shared caching of on-chip data. Our data-centric approach relies on in-hardware runtime profiling of the locality of data blocks and only allows private caching for data with high spatio-temporal locality. This allows us to better exploit on-chip cache capacity and enable low-latency, low-energy memory access, while retaining the convenience of shared memory. Tilera’s multicores have already demonstrated 20 Gbps pattern matching capabilities for network packet processing at 20 Watts of power. Using simulation models, our goal is to demonstrate 50 Gbps network traffic classification and flow features extraction at 10 Watts of power.

 

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